The present invention is directed, in general, to a method of fabricating a semiconductor device and, more specifically, to a semiconductor device having multilevel interconnections and a method of manufacture thereof.
The semiconductor industry is currently moving toward low dielectric constant (low-k) materials and copper metal to form interconnections for semiconductor devices to reduce resistive capacitance delays associated with the higher dielectric constant of silicon dioxide. These low-k materials also are used to reduce RC delays of aluminum interconnections and higher densities of a is conductor per unit are of the device. Furthermore, industry is presently moving away from metal etching of conductor lines followed by gap-fill with a low-k dielectric because copper metal is difficult to etch. In place of these processes, the industry has adopted damascene strategies for fabricating these interconnections that first etch patterns into the low-k material and then fills the structures with metal. Damascene processing has fewer manufacturing steps per completed metal layer, and considering that devices of the near future will require as many as seven inter-level connections, such as vias, and a corresponding number of intra-level connections, such as wires or lines, damascene processing should lead to considerable cost and performance gains over traditional interconnect processing. Additionally, dual damascene strategies where both the via and wire are patterned simultaneously etched and simultaneously filled with metal, further reducing the number of processing steps.
These damascene processes are not without their problems, however. Some of those problems arise with respect to the use of hard masks and critical dimension control. In the damascene approach as line widths shrink, it has become increasingly difficult to apply a copper seed layer to allow a complete fill by electroplating processes. Furthermore, during etching of the damascene structures, the selectivity of etching low-k materials, which are frequently polymeric materials, in the presence of photoresist is poor and requires inorganic dielectric etch stops to allow for over-etching and resist strip. During etching, there is a danger of undercutting the hard mask forming an area that is difficult to completely cover in subsequent deposition processes, resulting in a void. Thus, deposition of barriers to prevent copper diffusion and deposition of copper seed for electroplating are difficult processing steps, particularly given the high aspect ratios associated with today""s submicron technologies that are less than 0.25 xcexcm. Because of these high aspect ratios, the step coverage of severe topography is frequently insufficient and results in incomplete coverage of the feature sidewalls and bottom that leads to thin or missing barrier material and copper seed resulting in barrier failure or void formation during plating. Also, void-free fill of metal by electroplating is difficult since plating tends to cover topography conformally leading to a seam in the center of the feature. This can form a region of high electromigration probability that reduces device reliability. Additionally, the seam-void can also act as a trap for liquid plating solution that can xe2x80x9cexplodexe2x80x9d during subsequent processing steps that achieve temperatures above the boiling point of the trapped liquid. Since plating tends to occur conformally, areas with a high density of small features tend to fill faster than larger open areas. As a result metal, must be plated to a thickness at least as the depth of the largest feature. This forms topography of varying heights that are difficult to planarize with chemical mechanical polishing (CMP) processes.
Accordingly, what is needed in the art is a method and resulting device that avoid the problems associated with the above-discussed processes.
To address the above-discussed deficiencies of the prior art, the present invention provides, in one aspect, a method for fabricating an interconnect system within a semiconductor device. In this particular embodiment, the method comprises forming a conductive layer over a substrate of the semiconductor device, such as a dielectric material, forming a photoresist layer over the conductive layer and patterning the photoresist, forming a selected portion and an unselected portion of the conductive layer, altering the selected portion such that the selected portion has an etch rate different from an etch rate of the unselected portion, and forming an interconnect on the selected or unselected portion. As used herein, the selected portion is defined as that portion of the conductive layer, such as a blanket seed layer, that is subject to the alteration process as discussed herein. The selected portion may be, depending on the embodiment, within a footprint of the interconnect or outside the footprint of the interconnect. The interconnect structure formed by the present invention includes interconnect lines, contact plugs or metal filled interconnect vias.
Thus in a broad scope, the present invention provides a method of uniformly forming a conductive layer on which an interconnect is formed within a patterned photoresist. Because of the uniformity with which the conductive layer is formed and its presence only at the bottom of the pattern, problems, such as the occurrence of voids within the interconnect, that arise due to conformal plating of aspect ratios associated with present day and future submicron technologies can be avoided, thereby, providing a more reliable interconnect within a semiconductor device. Moreover, the present invention eliminates the need for critical etches and highly conformal seed for electroplating.
In one embodiment, forming an interconnect on the selected portion includes forming an interconnect on the selected portion and the method further comprises removing a substantial portion of the unselected portion from a region around the interconnect. The term xe2x80x9csubstantialxe2x80x9d as used herein is used to account for unintentional trace amounts that might remain due to inefficiencies in the removal process. In this embodiment, the selected portion is subjected to the alteration process wherein its etch rate is altered to have an etch rate less than an etch rate of the unselected portion. Thus, the unselected portion is more easily removed by the etching process.
In another embodiment, forming an interconnect includes forming an interconnect on the unselected portion and the method further comprises removing a substantial portion of the selected portion from a region around and outside of the interconnect""s footprint. In this embodiment, the selected portion is subjected to the alteration process wherein its etch rate is altered to have an etch rate greater than an etch rate of the unselected portion. Thus, the selected portion is more easily removed by the etching process.
Various processes may be used to alter the selected portions of the conductive layer. For example, the process may include subjecting the selected portion to an ion bombardment process, or, the process may include subjecting the selected portion to a nitridation, oxidation or halogenation processes. Alternatively, altering may include alloying and forming compositions of the selected portion with another metal from Groups IIA-VA or a transition metal or a lanthanide metal. Compositions of the selected portion and the interconnect metal are particularly advantageous. In such embodiments, the interconnect metal and the conductive layer should be chosen so that they will interdiffuse or alloy under the desired processing conditions. For example, the conductive layer metal may be Group II metals, such as magnesium, or antimony. Other exemplary conductive layer metals may include titanium, zirconium, zinc, tin, lead, niobium, chromium, molybdenum europium, tungsten, palladium, or aluminum when the metal used to form the interconnect is copper or silver. Yet other metals may include Group VA metals, such as antimony, transition metals, such as tungsten or lanthanide metals, such as neodymium. In yet another aspect of this particular embodiment, forming an alloy may also include forming a diffusion barrier to prevent interconnect metal from diffusing into materials that contact the interconnect.
Altering may also include interdiffusing the selected portion and the interconnect. Preferably, the interdiffusion forms a barrier layer between the interconnect and surrounding dielectric.
In another embodiment, the method further comprises removing the photoresist and the unselected portion outside a footprint of the interconnect and forming a dielectric layer over the interconnect subsequent to removing the photoresist and the unselected portion outside the footprint. The dielectric layer may be deposited by a vapor or liquid and may be comprised of a homogeneous or heterogeneous composition. In another embodiment, forming and patterning the photoresist layer includes forming a seed layer that comprises the metal used to form the interconnect by a directional deposition process.
In those embodiments where the interconnect is formed on a dielectric material, forming the conductive layer includes forming the conductive layer in such a way as to form a barrier layer between the interconnect and the substrate.
The present invention provides yet another unique aspect of forming an interconnect. In this particular embodiment, forming an interconnect includes forming a suspended, multilevel interconnect that is preferably formed on a single conductive layer. This particular embodiment may further include forming a barrier layer between the interconnect and the substrate. In one aspect of this particular advantageous embodiment, forming the suspended interconnect includes forming and patterning a subsequent photoresist layer on the interconnect, forming a subsequent interconnect pattern on or in the subsequent photoresist layer such that the subsequent interconnect physically contacts the interconnect. After the formation of the interconnect, the photoresist and the subsequent photoresist are simultaneously removed. In another aspect, the method further comprises simultaneously forming with the suspended interconnect, a support structure for the suspended interconnect.
In another aspect, the present invention provides a method for fabricating a semiconductor device, on a semiconductor wafer. In this particular embodiment, the method includes forming a dielectric layer over an active device formed on the semiconductor wafer, forming a blanket conductive seed layer over the dielectric layer, forming a photoresist layer over the conductive seed layer and patterning the photoresist, forming a selected portion and an unselected portion of the conductive seed layer, altering the selected portion such that the selected portion has an etch rate different from an etch rate of the unselected portion, and forming an interconnect on the selected or unselected portion.
Another embodiment is directed to a semiconductor device that includes an active device region, a blanket, conductive layer formed over the active device region, and a suspended interconnect formed on the conductive layer as is discussed below. In this particular embodiment, the device further includes a suspended interconnect support structure, such as a bond pad, that is electrically connected to the suspended interconnect. This embodiment may further include a plurality of electrically connected interconnect lines, contact plugs, or metal filled vias formed on different levels of the semiconductor device. The various levels of interconnect structure may be electrically isolated by a gaseous dielectric, such as a rare gas, nitrogen, forming gas, sulfur hexafluoride, or vacuum, in place of conventional dielectric materials. Preferably, the dielectric has a dielectric constant of less than about 2.3.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form. dr
For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
FIG. 1 illustrates a schematic sectional view of an active device having a uniform blanket conductive layer and a photoresist formed thereon;
FIG. 2 illustrates an enlarged sectional view of a top section of FIG. 1 showing a selected portion of the conductive layer;
FIG. 3 illustrates the selected portion of FIG. 2 following plating that contacts the underlying metal through the blanket conductive layer;
FIG. 4 illustrates the interconnect of FIG. 3 after the removal of the photoresist;
FIG. 5 illustrates the interconnect of FIG. 4 after the removal of the portion of the conductive layer outside the footprint of the interconnect metal;
FIG. 6 illustrates a barrier layer formed over the interconnect of FIG. 5;
FIG. 7 illustrates the barrier layer and interconnect of FIG. 6 after a directional sputter/etch;
FIG. 8 illustrates the barrier layer and interconnect of FIG. 7 after the deposition and planarization of an intra metal dielectric;
FIG. 9 illustrates the structure of FIG. 8 after the deposition of a subsequent conductive layer;
FIG. 10A illustrates the structure of FIG. 9 after depositing and patterning a subsequent layer of photoresist and altering the selected portion;
FIG. 10B illustrates the structure of FIG. 10A after formation of a subsequent interconnect ion metal, removal of photoresist and removal of the conductive layer outside the footprint of the interconnect metal;
FIG. 11A illustrates a sectional view of a suspended interconnect structure;
FIGS. 11B-11E illustrate sectional views of various intermediate steps during the formation of the suspended interconnect structure of FIG. 11A;
FIG. 12 illustrates a flow chart for process forming multilevel suspended interconnect structures;
FIG. 13 illustrates a flow chart for process forming multi levels with intra metal dielectric one layer at a time.